/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  Can_IP_Reg.h
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL Can Driver.
 */
#ifndef CAN_IP_REG_H_
#define CAN_IP_REG_H_

#ifdef __cplusplus
extern "C" {
#define   I__     volatile
#else
#define   I__     volatile const
#endif
/* Version and Check Begin */
/* Version Info Begin */
#define CAN_IP_REG_H_VENDOR_ID    0x8C
#define CAN_IP_REG_H_AR_RELEASE_MAJOR_VERSION    4
#define CAN_IP_REG_H_AR_RELEASE_MINOR_VERSION    3
#define CAN_IP_REG_H_AR_RELEASE_REVISION_VERSION 1
#define CAN_IP_REG_H_SW_MAJOR_VERSION    1
#define CAN_IP_REG_H_SW_MINOR_VERSION    0
#define CAN_IP_REG_H_SW_PATCH_VERSION    0
/* Version Info End */
/* Version and Check End */ /* __cplusplus */
#define     O__     volatile
#define     IO__    volatile

/** CAN - Register Layout Typedef */
typedef struct
{
    IO__ uint32 MCR;                               /*Module Configuration Register, offset: 0x0 */
    IO__ uint32 CTRL1;                             /*Control 1 register, offset: 0x4 */
    IO__ uint32 TIMER;                             /*Free Running Timer, offset: 0x8 */
    uint8 RESERVED_0[4];
    IO__ uint32
    RXMGMASK;                          /*Rx Mailboxes Global Mask Register, offset: 0x10 */
    IO__ uint32 RX14MASK;                          /*Rx 14 Mask register, offset: 0x14 */
    IO__ uint32 RX15MASK;                          /*Rx 15 Mask register, offset: 0x18 */
    IO__ uint32 ECR;                               /*Error Counter, offset: 0x1C */
    IO__ uint32 ESR1;                              /*Error and Status 1 register, offset: 0x20 */
    IO__ uint32 IMASK2;                            /*Interrupt Masks 2 register, offset: 0x24 */
    IO__ uint32 IMASK1;                            /*Interrupt Masks 1 register, offset: 0x28 */
    IO__ uint32 IFLAG2;                            /*Interrupt Flags 2 register, offset: 0x2C */
    IO__ uint32 IFLAG1;                            /*Interrupt Flags 1 register, offset: 0x30 */
    IO__ uint32 CTRL2;                             /*Control 2 register, offset: 0x34 */
    I__  uint32 ESR2;                              /*Error and Status 2 register, offset: 0x38 */
    uint8 RESERVED_1[8];
    I__  uint32 CRCR;                              /*CRC Register, offset: 0x44 */
    IO__ uint32 RXFGMASK;                          /*Rx FIFO Global Mask register, offset: 0x48 */
    I__  uint32 RXFIR;                             /*Rx FIFO Information Register, offset: 0x4C */
    IO__ uint32 CBT;                               /*CAN Bit Timing Register, offset: 0x50 */
    uint8 RESERVED_2[20];
    IO__ uint32 IMASK4;                            /*Interrupt Masks 4 register, offset: 0x68 */
    IO__ uint32 IMASK3;                            /*Interrupt Masks 3 register, offset: 0x6C */
    IO__ uint32 IFLAG4;                            /*Interrupt Flags 4 register, offset: 0x70 */
    IO__ uint32 IFLAG3;                            /*Interrupt Flags 3 register, offset: 0x74 */
    uint8 RESERVED_3[8];
    struct                                         /* offset: 0x80, array step: 0x10 */
    {
        IO__ uint32
        CS;                            /*Message Buffer 0 CS Register..Message Buffer 127 CS Register, array offset: 0x80, array step: 0x10 */
        IO__ uint32
        ID;                            /*Message Buffer 0 ID Register..Message Buffer 127 ID Register, array offset: 0x84, array step: 0x10 */
        IO__ uint32
        WORD0;                         /*Message Buffer 0 WORD0 Register..Message Buffer 127 WORD0 Register, array offset: 0x88, array step: 0x10 */
        IO__ uint32
        WORD1;                         /*Message Buffer 0 WORD1 Register..Message Buffer 127 WORD1 Register, array offset: 0x8C, array step: 0x10 */
    } MB[128];
    IO__ uint32
    RXIMR[128];                        /*Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
    uint32 RESERVED_4[24];             /*  96Byte */
    IO__ uint32 MECR;                              /*Memory Error Control Register, offset: 0xAE0 */
    IO__ uint32
    ERRIAR;                            /*Error Injection Address Register, offset: 0xAE4 */
    IO__ uint32
    ERRIDPR;                           /*Error Injection Data Pattern Register, offset: 0xAE8 */
    IO__ uint32
    ERRIPPR;                           /*Error Injection Parity Pattern Register, offset: 0xAEC */
    I__  uint32 RERRAR;                            /*Error Report Address Register, offset: 0xAF0 */
    I__  uint32 RERRDR;                            /*Error Report Data Register, offset: 0xAF4 */
    I__  uint32 RERRSYNR;                          /*Error Report Syndrome Register, offset: 0xAF8 */
    IO__ uint32 ERRSR;                             /*Error Status Register, offset: 0xAFC */
    IO__ uint32
    CTRL1_PN;                          /*Pretended Networking Control 1 Register, offset: 0xB00 */
    IO__ uint32
    CTRL2_PN;                          /*Pretended Networking Control 2 Register, offset: 0xB04 */
    IO__ uint32
    WU_MTC;                            /*Pretended Networking Wake Up Match Register, offset: 0xB08 */
    IO__ uint32
    FLT_ID1;                           /*Pretended Networking ID Filter 1 Register, offset: 0xB0C */
    IO__ uint32
    FLT_DLC;                           /*Pretended Networking DLC Filter Register, offset: 0xB10 */
    IO__ uint32
    PL1_LO;                            /*Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */
    IO__ uint32
    PL1_HI;                            /*Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */
    IO__ uint32
    FLT_ID2_IDMASK;                    /*Pretended Networking ID Filter 2 Register/ ID Mask Register, offset: 0xB1C */
    IO__ uint32
    PL2_PLMASK_LO;                     /*Pretended Networking Payload Low Filter 2 Register/ Payload Low Mask Register, offset: 0xB20 */
    IO__ uint32
    PL2_PLMASK_HI;                     /*Pretended Networking Payload High Filter 2 High Order Bits/ Payload High Mask Register, offset: 0xB24 */
    uint8 RESERVED_5[24];
    struct                                         /* offset: 0xB40, array step: 0x10 */
    {
        I__  uint32
        WMB_CS;                        /*Wake Up Message Buffer Register for C/S, offset: 0xB40, array step: 0x10 */
        I__  uint32
        WMB_ID;                        /*Wake Up Message Buffer Register for ID, offset: 0xB44, array step: 0x10 */
        I__  uint32
        WMB_D03;                       /*Wake Up Message Buffer Register for Data 0-3, offset: 0xB48, array step: 0x10 */
        I__  uint32
        WMB_D47;                       /*Wake Up Message Buffer Register for Data 4-7, offset: 0xB4C, array step: 0x10 */
    } WMB[4];
    uint8 RESERVED_6[112];
    IO__ uint32 EPRS; /*Enhanced CAN Bit Timing Prescalers Register, offset: 0xBF0 */
    IO__ uint32 ENCBT;  /*Enhanced Nominal CAN Bit Timing Register, offset: 0xBF4 */
    IO__ uint32 EDCBT;   /*Enhanced Data Phase CAN Bit Timing Register, offset: 0xBF8 */
    IO__ uint32 ETDC;   /*Enhanced Transceiver Delay Compensation Register, offset: 0xBFC */
    IO__ uint32 FDCTRL; /*The CAN_FDCTRL register contains control bits for CAN FD operation, offset: 0xC00 */
    IO__ uint32 FDCBT;  /*The CAN_FDCBT register stores the CAN bit timing variables , offset: 0xC04 */
    I__ uint32 FDCRC;   /*The CAN_CRCR register provides information about the CRC of transmitted
    messages for non-FD messages., offset: 0xC08 */
    IO__ uint32
    ERFCR;                             /*Enhanced CAN Rx FIFO Control Register, offset: 0xC0C */
    IO__ uint32
    ERFIER;                            /*Enhanced CAN Rx FIFO Interrupt Enable register, offset: 0xC10 */
    IO__ uint32
    ERFSR;                             /*Enhanced CAN Rx FIFO Status Register, offset: 0xC14 */
    uint8 RESERVED_7[24];
    I__  uint32
    HR_TIME_STAMP[64];                 /*CAN High Resolution Time Stamp, offset: 0xC30 */
    uint8 RESERVED_8[8912];
    IO__ uint32
    ERFFEL[128];                       /*Enhanced CAN Rx FIFO Filter Elements, offset: 0x3000 */
    uint8 RESERVED_9[12];
    IO__ uint32 ERR_IRQ_STATUS;    /*Function Safety Error Interrupt Status
                                        Register, offset: 0x320C */
    IO__ uint32 ERR_IRQ_STATUS_EN; /*Safety Error Interrupt Status Enable
                                        Register, offset: 0x3210 */
    IO__ uint32 ERR_IRQ_SIG_EN;    /*Safety Error Interrupt Signal Enable
                                        Register, offset: 0x3214 */
    uint8 RESERVED_10[20];
    IO__ uint32 LOWPOWER_MODE; /*LOWPOWER_MODE Register, offset:0x322C */
    uint8 RESERVED_11[24];
    IO__ uint32
    GLITCH_FILTER_CONFIG; /*CANFD glitch filter configuration for stop
                                 and doze feature Register, offset: 0x3248 */
    IO__ uint32 SOFT_RESET; /*CANFD Soft Reset register, offset: 0x324C */
    IO__ uint32 CAN_INFO; /*FLEXCAN INFO register, offset: 0x3250 */
} Can_RegType;


#define FLEXCAN_MCR_MAXMB_MASK                       (0x7FU)         /* Mask for the MAXMB field */
#define FLEXCAN_MCR_MAXMB_SHIFT                      (0U)            /* Shift value for the MAXMB field */
#define FLEXCAN_MCR_MAXMB(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_MCR_MAXMB_SHIFT)) & FLEXCAN_MCR_MAXMB_MASK) /* Constructs the MAXMB field value */
/*
 *  This field defines the maximum number of mailboxes in the CAN module.
 */
#define FLEXCAN_MCR_IDAM_MASK                        (0x300U)        /* Mask for the IDAM field */
#define FLEXCAN_MCR_IDAM_SHIFT                       (8U)            /* Shift value for the IDAM field */
#define FLEXCAN_MCR_IDAM(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_IDAM_SHIFT)) & FLEXCAN_MCR_IDAM_MASK) /* Constructs the IDAM field value */
/*
 *  This field configures the ID acceptance mode for the CAN module.
 */
#define FLEXCAN_MCR_FDEN_MASK                        (0x800U)        /* Mask for the FDEN field */
#define FLEXCAN_MCR_FDEN_SHIFT                       (11U)           /* Shift value for the FDEN field */
#define FLEXCAN_MCR_FDEN(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_FDEN_SHIFT)) & FLEXCAN_MCR_FDEN_MASK) /* Constructs the FDEN field value */
/*
 *  This bit enables or disables the CAN FD (Flexible Data-rate) feature.
 */
#define FLEXCAN_MCR_AEN_MASK                         (0x1000U)       /* Mask for the AEN field */
#define FLEXCAN_MCR_AEN_SHIFT                        (12U)           /* Shift value for the AEN field */
#define FLEXCAN_MCR_AEN(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_MCR_AEN_SHIFT)) & FLEXCAN_MCR_AEN_MASK) /* Constructs the AEN field value */
/*
 *  This bit enables or disables the abort feature for message transmission.
 */
#define FLEXCAN_MCR_LPRIOEN_MASK                     (0x2000U)       /* Mask for the LPRIOEN field */
#define FLEXCAN_MCR_LPRIOEN_SHIFT                    (13U)           /* Shift value for the LPRIOEN field */
#define FLEXCAN_MCR_LPRIOEN(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK) /* Constructs the LPRIOEN field value */
/*
 *  This bit enables or disables the local priority feature for message transmission.
 */
#define FLEXCAN_MCR_DMA_MASK                         (0x8000U)       /* Mask for the DMA field */
#define FLEXCAN_MCR_DMA_SHIFT                        (15U)           /* Shift value for the DMA field */
#define FLEXCAN_MCR_DMA(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_MCR_DMA_SHIFT)) & FLEXCAN_MCR_DMA_MASK) /* Constructs the DMA field value */
/*
 *  This bit enables or disables the DMA feature for the CAN module.
 */
#define FLEXCAN_MCR_IRMQ_MASK                        (0x10000U)      /* Mask for the IRMQ field */
#define FLEXCAN_MCR_IRMQ_SHIFT                       (16U)           /* Shift value for the IRMQ field */
#define FLEXCAN_MCR_IRMQ(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_IRMQ_SHIFT)) & FLEXCAN_MCR_IRMQ_MASK) /* Constructs the IRMQ field value */
/*
 *  This bit enables or disables individual Rx masking and queue features.
 */
#define FLEXCAN_MCR_SRXDIS_MASK                      (0x20000U)      /* Mask for the SRXDIS field */
#define FLEXCAN_MCR_SRXDIS_SHIFT                     (17U)           /* Shift value for the SRXDIS field */
#define FLEXCAN_MCR_SRXDIS(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_SRXDIS_SHIFT)) & FLEXCAN_MCR_SRXDIS_MASK) /* Constructs the SRXDIS field value */
/*
 *  This bit disables the self-reception feature.
 */
#define FLEXCAN_MCR_DOZE_MASK                        (0x40000U)      /* Mask for the DOZE field */
#define FLEXCAN_MCR_DOZE_SHIFT                       (18U)           /* Shift value for the DOZE field */
#define FLEXCAN_MCR_DOZE(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_DOZE_SHIFT)) & FLEXCAN_MCR_DOZE_MASK) /* Constructs the DOZE field value */
/*
 *  This bit enables or disables the doze mode for power saving.
 */
#define FLEXCAN_MCR_WAKSRC_MASK                      (0x80000U)      /* Mask for the WAKSRC field */
#define FLEXCAN_MCR_WAKSRC_SHIFT                     (19U)           /* Shift value for the WAKSRC field */
#define FLEXCAN_MCR_WAKSRC(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_WAKSRC_SHIFT)) & FLEXCAN_MCR_WAKSRC_MASK) /* Constructs the WAKSRC field value */
/*
 *  This bit selects the wake-up source for the CAN module.
 */
#define FLEXCAN_MCR_LPMACK_MASK                      (0x100000U)     /* Mask for the LPMACK field */
#define FLEXCAN_MCR_LPMACK_SHIFT                     (20U)           /* Shift value for the LPMACK field */
#define FLEXCAN_MCR_LPMACK(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_LPMACK_SHIFT)) & FLEXCAN_MCR_LPMACK_MASK) /* Constructs the LPMACK field value */
/*
 *  This bit indicates the acknowledgment of low power mode.
 */
#define FLEXCAN_MCR_WRNEN_MASK                       (0x200000U)     /* Mask for the WRNEN field */
#define FLEXCAN_MCR_WRNEN_SHIFT                      (21U)           /* Shift value for the WRNEN field */
#define FLEXCAN_MCR_WRNEN(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_MCR_WRNEN_SHIFT)) & FLEXCAN_MCR_WRNEN_MASK) /* Constructs the WRNEN field value */
/*
 *  This bit enables or disables the warning interrupt.
 */
#define FLEXCAN_MCR_SLFWAK_MASK                      (0x400000U)     /* Mask for the SLFWAK field */
#define FLEXCAN_MCR_SLFWAK_SHIFT                     (22U)           /* Shift value for the SLFWAK field */
#define FLEXCAN_MCR_SLFWAK(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_SLFWAK_SHIFT)) & FLEXCAN_MCR_SLFWAK_MASK) /* Constructs the SLFWAK field value */
/*
 *  This bit enables or disables the self wake-up feature.
 */
#define FLEXCAN_MCR_SUPV_MASK                        (0x800000U)     /* Mask for the SUPV field */
#define FLEXCAN_MCR_SUPV_SHIFT                       (23U)           /* Shift value for the SUPV field */
#define FLEXCAN_MCR_SUPV(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_SUPV_SHIFT)) & FLEXCAN_MCR_SUPV_MASK) /* Constructs the SUPV field value */
/*
 *  This bit sets the CAN module to supervisor mode.
 */
#define FLEXCAN_MCR_FRZACK_MASK                      (0x1000000U)    /* Mask for the FRZACK field */
#define FLEXCAN_MCR_FRZACK_SHIFT                     (24U)           /* Shift value for the FRZACK field */
#define FLEXCAN_MCR_FRZACK(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_FRZACK_SHIFT)) & FLEXCAN_MCR_FRZACK_MASK) /* Constructs the FRZACK field value */
/*
 *  This bit indicates the acknowledgment of freeze mode.
 */
#define FLEXCAN_MCR_SOFTRST_MASK                     (0x2000000U)    /* Mask for the SOFTRST field */
#define FLEXCAN_MCR_SOFTRST_SHIFT                    (25U)           /* Shift value for the SOFTRST field */
#define FLEXCAN_MCR_SOFTRST(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_MCR_SOFTRST_SHIFT)) & FLEXCAN_MCR_SOFTRST_MASK) /* Constructs the SOFTRST field value */
/*
 *  This bit triggers a soft reset of the CAN module.
 */
#define FLEXCAN_MCR_WAKMSK_MASK                      (0x4000000U)    /* Mask for the WAKMSK field */
#define FLEXCAN_MCR_WAKMSK_SHIFT                     (26U)           /* Shift value for the WAKMSK field */
#define FLEXCAN_MCR_WAKMSK(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_WAKMSK_SHIFT)) & FLEXCAN_MCR_WAKMSK_MASK) /* Constructs the WAKMSK field value */
/*
 *  This bit masks the wake-up interrupt.
 */
#define FLEXCAN_MCR_NOTRDY_MASK                      (0x8000000U)    /* Mask for the NOTRDY field */
#define FLEXCAN_MCR_NOTRDY_SHIFT                     (27U)           /* Shift value for the NOTRDY field */
#define FLEXCAN_MCR_NOTRDY(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_MCR_NOTRDY_SHIFT)) & FLEXCAN_MCR_NOTRDY_MASK) /* Constructs the NOTRDY field value */
/*
 *  This bit indicates that the CAN module is not ready.
 */
#define FLEXCAN_MCR_HALT_MASK                        (0x10000000U)   /* Mask for the HALT field */
#define FLEXCAN_MCR_HALT_SHIFT                       (28U)           /* Shift value for the HALT field */
#define FLEXCAN_MCR_HALT(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_HALT_SHIFT)) & FLEXCAN_MCR_HALT_MASK) /* Constructs the HALT field value */
/*
 *  This bit halts the CAN module.
 */
#define FLEXCAN_MCR_RFEN_MASK                        (0x20000000U)   /* Mask for the RFEN field */
#define FLEXCAN_MCR_RFEN_SHIFT                       (29U)           /* Shift value for the RFEN field */
#define FLEXCAN_MCR_RFEN(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_RFEN_SHIFT)) & FLEXCAN_MCR_RFEN_MASK) /* Constructs the RFEN field value */
/*
 *  This bit enables or disables the Rx FIFO.
 */
#define FLEXCAN_MCR_FRZ_MASK                         (0x40000000U)   /* Mask for the FRZ field */
#define FLEXCAN_MCR_FRZ_SHIFT                        (30U)           /* Shift value for the FRZ field */
#define FLEXCAN_MCR_FRZ(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_MCR_FRZ_SHIFT)) & FLEXCAN_MCR_FRZ_MASK) /* Constructs the FRZ field value */
/*
 *  This bit sets the CAN module to freeze mode.
 */
#define FLEXCAN_MCR_MDIS_MASK                        (0x80000000U)   /* Mask for the MDIS field */
#define FLEXCAN_MCR_MDIS_SHIFT                       (31U)           /* Shift value for the MDIS field */
#define FLEXCAN_MCR_MDIS(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_MCR_MDIS_SHIFT)) & FLEXCAN_MCR_MDIS_MASK) /* Constructs the MDIS field value */
/*
 *  This bit disables the CAN module.
 */



#define FLEXCAN_CTRL1_PROPSEG_MASK                   (0x7U)          /* Mask for the PROPSEG field */
#define FLEXCAN_CTRL1_PROPSEG_SHIFT                  (0U)            /* Shift value for the PROPSEG field */
#define FLEXCAN_CTRL1_PROPSEG(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK) /* Constructs the PROPSEG field value */
/*
 *  This field defines the length of the propagation segment in the bit time.
 */
#define FLEXCAN_CTRL1_LOM_MASK                       (0x8U)          /* Mask for the LOM field */
#define FLEXCAN_CTRL1_LOM_SHIFT                      (3U)            /* Shift value for the LOM field */
#define FLEXCAN_CTRL1_LOM(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_LOM_SHIFT)) & FLEXCAN_CTRL1_LOM_MASK) /* Constructs the LOM field value */
/*
 *  This bit sets the CAN module to listen-only mode.
 */
#define FLEXCAN_CTRL1_LBUF_MASK                      (0x10U)         /* Mask for the LBUF field */
#define FLEXCAN_CTRL1_LBUF_SHIFT                     (4U)            /* Shift value for the LBUF field */
#define FLEXCAN_CTRL1_LBUF(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_LBUF_SHIFT)) & FLEXCAN_CTRL1_LBUF_MASK) /* Constructs the LBUF field value */
/*
 *  This bit configures the transmission order of the buffers.
 */
#define FLEXCAN_CTRL1_TSYN_MASK                      (0x20U)         /* Mask for the TSYN field */
#define FLEXCAN_CTRL1_TSYN_SHIFT                     (5U)            /* Shift value for the TSYN field */
#define FLEXCAN_CTRL1_TSYN(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_TSYN_SHIFT)) & FLEXCAN_CTRL1_TSYN_MASK) /* Constructs the TSYN field value */
/*
 *  This bit enables or disables the timer synchronization feature.
 */
#define FLEXCAN_CTRL1_BOFFREC_MASK                   (0x40U)         /* Mask for the BOFFREC field */
#define FLEXCAN_CTRL1_BOFFREC_SHIFT                  (6U)            /* Shift value for the BOFFREC field */
#define FLEXCAN_CTRL1_BOFFREC(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_BOFFREC_SHIFT)) & FLEXCAN_CTRL1_BOFFREC_MASK) /* Constructs the BOFFREC field value */
/*
 *  This bit configures the bus off recovery behavior.
 */
#define FLEXCAN_CTRL1_SMP_MASK                       (0x80U)         /* Mask for the SMP field */
#define FLEXCAN_CTRL1_SMP_SHIFT                      (7U)            /* Shift value for the SMP field */
#define FLEXCAN_CTRL1_SMP(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_SMP_SHIFT)) & FLEXCAN_CTRL1_SMP_MASK) /* Constructs the SMP field value */
/*
 *  This bit configures the sampling mode for the CAN module.
 */
#define FLEXCAN_CTRL1_RWRNMSK_MASK                   (0x400U)        /* Mask for the RWRNMSK field */
#define FLEXCAN_CTRL1_RWRNMSK_SHIFT                  (10U)           /* Shift value for the RWRNMSK field */
#define FLEXCAN_CTRL1_RWRNMSK(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_RWRNMSK_SHIFT)) & FLEXCAN_CTRL1_RWRNMSK_MASK) /* Constructs the RWRNMSK field value */
/*
 *  This bit masks the Rx warning interrupt.
 */
#define FLEXCAN_CTRL1_TWRNMSK_MASK                   (0x800U)        /* Mask for the TWRNMSK field */
#define FLEXCAN_CTRL1_TWRNMSK_SHIFT                  (11U)           /* Shift value for the TWRNMSK field */
#define FLEXCAN_CTRL1_TWRNMSK(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_TWRNMSK_SHIFT)) & FLEXCAN_CTRL1_TWRNMSK_MASK) /* Constructs the TWRNMSK field value */
/*
 *  This bit masks the Tx warning interrupt.
 */
#define FLEXCAN_CTRL1_LPB_MASK                       (0x1000U)       /* Mask for the LPB field */
#define FLEXCAN_CTRL1_LPB_SHIFT                      (12U)           /* Shift value for the LPB field */
#define FLEXCAN_CTRL1_LPB(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_LPB_SHIFT)) & FLEXCAN_CTRL1_LPB_MASK) /* Constructs the LPB field value */
/*
 *  This bit enables or disables the loop back mode.
 */
#define FLEXCAN_CTRL1_MB07_ENHANCED_MASK             (0x2000U)       /* Mask for the MB07_ENHANCED field */
#define FLEXCAN_CTRL1_MB07_ENHANCED_SHIFT            (13U)           /* Shift value for the MB07_ENHANCED field */
#define FLEXCAN_CTRL1_MB07_ENHANCED(x)               (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_MB07_ENHANCED_SHIFT)) & FLEXCAN_CTRL1_MB07_ENHANCED_MASK) /* Constructs the MB07_ENHANCED field value */
/*
 *  This bit enables enhanced features for mailboxes 0 to 7.
 */
#define FLEXCAN_CTRL1_ERRMSK_MASK                    (0x4000U)       /* Mask for the ERRMSK field */
#define FLEXCAN_CTRL1_ERRMSK_SHIFT                   (14U)           /* Shift value for the ERRMSK field */
#define FLEXCAN_CTRL1_ERRMSK(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_ERRMSK_SHIFT)) & FLEXCAN_CTRL1_ERRMSK_MASK) /* Constructs the ERRMSK field value */
/*
 *  This bit masks the error interrupt.
 */
#define FLEXCAN_CTRL1_BOFFMSK_MASK                   (0x8000U)       /* Mask for the BOFFMSK field */
#define FLEXCAN_CTRL1_BOFFMSK_SHIFT                  (15U)           /* Shift value for the BOFFMSK field */
#define FLEXCAN_CTRL1_BOFFMSK(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_BOFFMSK_SHIFT)) & FLEXCAN_CTRL1_BOFFMSK_MASK) /* Constructs the BOFFMSK field value */
/*
 *  This bit masks the bus off interrupt.
 */
#define FLEXCAN_CTRL1_PSEG2_MASK                     (0x70000U)      /* Mask for the PSEG2 field */
#define FLEXCAN_CTRL1_PSEG2_SHIFT                    (16U)           /* Shift value for the PSEG2 field */
#define FLEXCAN_CTRL1_PSEG2(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK) /* Constructs the PSEG2 field value */
/*
 *  This field defines the length of phase segment 2 in the bit time.
 */
#define FLEXCAN_CTRL1_PSEG1_MASK                     (0x380000U)     /* Mask for the PSEG1 field */
#define FLEXCAN_CTRL1_PSEG1_SHIFT                    (19U)           /* Shift value for the PSEG1 field */
#define FLEXCAN_CTRL1_PSEG1(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK) /* Constructs the PSEG1 field value */
/*
 *  This field defines the length of phase segment 1 in the bit time.
 */
#define FLEXCAN_CTRL1_RJW_MASK                       (0xC00000U)     /* Mask for the RJW field */
#define FLEXCAN_CTRL1_RJW_SHIFT                      (22U)           /* Shift value for the RJW field */
#define FLEXCAN_CTRL1_RJW(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK) /* Constructs the RJW field value */
/*
 *  This field defines the resynchronization jump width.
 */
#define FLEXCAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)   /* Mask for the PRESDIV field */
#define FLEXCAN_CTRL1_PRESDIV_SHIFT                  (24U)           /* Shift value for the PRESDIV field */
#define FLEXCAN_CTRL1_PRESDIV(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK) /* Constructs the PRESDIV field value */
/*
 *  This field defines the prescaler division factor for the CAN clock.
 */



#define FLEXCAN_TIMER_TIMER_MASK                     (0xFFFFU)       /* Mask for the TIMER field */
#define FLEXCAN_TIMER_TIMER_SHIFT                    (0U)            /* Shift value for the TIMER field */
#define FLEXCAN_TIMER_TIMER(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_TIMER_TIMER_SHIFT)) & FLEXCAN_TIMER_TIMER_MASK) /* Constructs the TIMER field value */
/*
 *  This field holds the current value of the free running timer.
 */



#define FLEXCAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)   /* Mask for the MG field */
#define FLEXCAN_RXMGMASK_MG_SHIFT                    (0U)            /* Shift value for the MG field */
#define FLEXCAN_RXMGMASK_MG(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_RXMGMASK_MG_SHIFT)) & FLEXCAN_RXMGMASK_MG_MASK) /* Constructs the MG field value */
/*
 *  This register defines the global mask for Rx mailboxes.
 */



#define FLEXCAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)   /* Mask for the RX14M field */
#define FLEXCAN_RX14MASK_RX14M_SHIFT                 (0U)            /* Shift value for the RX14M field */
#define FLEXCAN_RX14MASK_RX14M(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_RX14MASK_RX14M_SHIFT)) & FLEXCAN_RX14MASK_RX14M_MASK) /* Constructs the RX14M field value */
/*
 *  This register defines the mask for Rx mailbox 14.
 */



#define FLEXCAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)   /* Mask for the RX15M field */
#define FLEXCAN_RX15MASK_RX15M_SHIFT                 (0U)            /* Shift value for the RX15M field */
#define FLEXCAN_RX15MASK_RX15M(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_RX15MASK_RX15M_SHIFT)) & FLEXCAN_RX15MASK_RX15M_MASK) /* Constructs the RX15M field value */
/*
 *  This register defines the mask for Rx mailbox 15.
 */



#define FLEXCAN_ECR_TXERRCNT_MASK                    (0xFFU)         /* Mask for the TXERRCNT field */
#define FLEXCAN_ECR_TXERRCNT_SHIFT                   (0U)            /* Shift value for the TXERRCNT field */
#define FLEXCAN_ECR_TXERRCNT(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK) /* Constructs the TXERRCNT field value */
/*
 *  This field holds the transmit error counter value.
 */
#define FLEXCAN_ECR_RXERRCNT_MASK                    (0xFF00U)       /* Mask for the RXERRCNT field */
#define FLEXCAN_ECR_RXERRCNT_SHIFT                   (8U)            /* Shift value for the RXERRCNT field */
#define FLEXCAN_ECR_RXERRCNT(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK) /* Constructs the RXERRCNT field value */
/*
 *  This field holds the receive error counter value.
 */



#define FLEXCAN_ESR1_WAKINT_MASK                     (0x1U)          /* Mask for the WAKINT field */
#define FLEXCAN_ESR1_WAKINT_SHIFT                    (0U)            /* Shift value for the WAKINT field */
#define FLEXCAN_ESR1_WAKINT(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_WAKINT_SHIFT)) & FLEXCAN_ESR1_WAKINT_MASK) /* Constructs the WAKINT field value */
/*
 *  This bit indicates a wake-up interrupt.
 */
#define FLEXCAN_ESR1_ERRINT_MASK                     (0x2U)          /* Mask for the ERRINT field */
#define FLEXCAN_ESR1_ERRINT_SHIFT                    (1U)            /* Shift value for the ERRINT field */
#define FLEXCAN_ESR1_ERRINT(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_ERRINT_SHIFT)) & FLEXCAN_ESR1_ERRINT_MASK) /* Constructs the ERRINT field value */
/*
 *  This bit indicates an error interrupt.
 */
#define FLEXCAN_ESR1_BOFFINT_MASK                    (0x4U)          /* Mask for the BOFFINT field */
#define FLEXCAN_ESR1_BOFFINT_SHIFT                   (2U)            /* Shift value for the BOFFINT field */
#define FLEXCAN_ESR1_BOFFINT(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_BOFFINT_SHIFT)) & FLEXCAN_ESR1_BOFFINT_MASK) /* Constructs the BOFFINT field value */
/*
 *  This bit indicates a bus off interrupt.
 */
#define FLEXCAN_ESR1_RX_MASK                         (0x8U)          /* Mask for the RX field */
#define FLEXCAN_ESR1_RX_SHIFT                        (3U)            /* Shift value for the RX field */
#define FLEXCAN_ESR1_RX(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_RX_SHIFT)) & FLEXCAN_ESR1_RX_MASK) /* Constructs the RX field value */
/*
 *  This bit indicates the receive status.
 */
#define FLEXCAN_ESR1_FLTCONF_MASK                    (0x30U)         /* Mask for the FLTCONF field */
#define FLEXCAN_ESR1_FLTCONF_SHIFT                   (4U)            /* Shift value for the FLTCONF field */
#define FLEXCAN_ESR1_FLTCONF(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_FLTCONF_SHIFT)) & FLEXCAN_ESR1_FLTCONF_MASK) /* Constructs the FLTCONF field value */
/*
 *  This field indicates the fault confinement state.
 */
#define FLEXCAN_ESR1_TX_MASK                         (0x40U)         /* Mask for the TX field */
#define FLEXCAN_ESR1_TX_SHIFT                        (6U)            /* Shift value for the TX field */
#define FLEXCAN_ESR1_TX(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_TX_SHIFT)) & FLEXCAN_ESR1_TX_MASK) /* Constructs the TX field value */
/*
 *  This bit indicates the transmit status.
 */
#define FLEXCAN_ESR1_IDLE_MASK                       (0x80U)         /* Mask for the IDLE field */
#define FLEXCAN_ESR1_IDLE_SHIFT                      (7U)            /* Shift value for the IDLE field */
#define FLEXCAN_ESR1_IDLE(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_IDLE_SHIFT)) & FLEXCAN_ESR1_IDLE_MASK) /* Constructs the IDLE field value */
/*
 *  This bit indicates the idle status.
 */
#define FLEXCAN_ESR1_RXWRN_MASK                      (0x100U)        /* Mask for the RXWRN field */
#define FLEXCAN_ESR1_RXWRN_SHIFT                     (8U)            /* Shift value for the RXWRN field */
#define FLEXCAN_ESR1_RXWRN(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_RXWRN_SHIFT)) & FLEXCAN_ESR1_RXWRN_MASK) /* Constructs the RXWRN field value */
/*
 *  This bit indicates a receive warning.
 */
#define FLEXCAN_ESR1_TXWRN_MASK                      (0x200U)        /* Mask for the TXWRN field */
#define FLEXCAN_ESR1_TXWRN_SHIFT                     (9U)            /* Shift value for the TXWRN field */
#define FLEXCAN_ESR1_TXWRN(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_TXWRN_SHIFT)) & FLEXCAN_ESR1_TXWRN_MASK) /* Constructs the TXWRN field value */
/*
 *  This bit indicates a transmit warning.
 */
#define FLEXCAN_ESR1_STFERR_MASK                     (0x400U)        /* Mask for the STFERR field */
#define FLEXCAN_ESR1_STFERR_SHIFT                    (10U)           /* Shift value for the STFERR field */
#define FLEXCAN_ESR1_STFERR(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_STFERR_SHIFT)) & FLEXCAN_ESR1_STFERR_MASK) /* Constructs the STFERR field value */
/*
 *  This bit indicates a stuffing error.
 */
#define FLEXCAN_ESR1_FRMERR_MASK                     (0x800U)        /* Mask for the FRMERR field */
#define FLEXCAN_ESR1_FRMERR_SHIFT                    (11U)           /* Shift value for the FRMERR field */
#define FLEXCAN_ESR1_FRMERR(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_FRMERR_SHIFT)) & FLEXCAN_ESR1_FRMERR_MASK) /* Constructs the FRMERR field value */
/*
 *  This bit indicates a form error.
 */
#define FLEXCAN_ESR1_CRCERR_MASK                     (0x1000U)       /* Mask for the CRCERR field */
#define FLEXCAN_ESR1_CRCERR_SHIFT                    (12U)           /* Shift value for the CRCERR field */
#define FLEXCAN_ESR1_CRCERR(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_CRCERR_SHIFT)) & FLEXCAN_ESR1_CRCERR_MASK) /* Constructs the CRCERR field value */
/*
 *  This bit indicates a CRC error.
 */
#define FLEXCAN_ESR1_ACKERR_MASK                     (0x2000U)       /* Mask for the ACKERR field */
#define FLEXCAN_ESR1_ACKERR_SHIFT                    (13U)           /* Shift value for the ACKERR field */
#define FLEXCAN_ESR1_ACKERR(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_ACKERR_SHIFT)) & FLEXCAN_ESR1_ACKERR_MASK) /* Constructs the ACKERR field value */
/*
 *  This bit indicates an acknowledge error.
 */
#define FLEXCAN_ESR1_BIT0ERR_MASK                    (0x4000U)       /* Mask for the BIT0ERR field */
#define FLEXCAN_ESR1_BIT0ERR_SHIFT                   (14U)           /* Shift value for the BIT0ERR field */
#define FLEXCAN_ESR1_BIT0ERR(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_BIT0ERR_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_MASK) /* Constructs the BIT0ERR field value */
/*
 *  This bit indicates a bit0 error.
 */
#define FLEXCAN_ESR1_BIT1ERR_MASK                    (0x8000U)       /* Mask for the BIT1ERR field */
#define FLEXCAN_ESR1_BIT1ERR_SHIFT                   (15U)           /* Shift value for the BIT1ERR field */
#define FLEXCAN_ESR1_BIT1ERR(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_BIT1ERR_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_MASK) /* Constructs the BIT1ERR field value */
/*
 *  This bit indicates a bit1 error.
 */
#define FLEXCAN_ESR1_RWRNINT_MASK                    (0x10000U)      /* Mask for the RWRNINT field */
#define FLEXCAN_ESR1_RWRNINT_SHIFT                   (16U)           /* Shift value for the RWRNINT field */
#define FLEXCAN_ESR1_RWRNINT(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_RWRNINT_SHIFT)) & FLEXCAN_ESR1_RWRNINT_MASK) /* Constructs the RWRNINT field value */
/*
 *  This bit indicates a receive warning interrupt.
 */
#define FLEXCAN_ESR1_TWRNINT_MASK                    (0x20000U)      /* Mask for the TWRNINT field */
#define FLEXCAN_ESR1_TWRNINT_SHIFT                   (17U)           /* Shift value for the TWRNINT field */
#define FLEXCAN_ESR1_TWRNINT(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_TWRNINT_SHIFT)) & FLEXCAN_ESR1_TWRNINT_MASK) /* Constructs the TWRNINT field value */
/*
 *  This bit indicates a transmit warning interrupt.
 */
#define FLEXCAN_ESR1_SYNCH_MASK                      (0x40000U)      /* Mask for the SYNCH field */
#define FLEXCAN_ESR1_SYNCH_SHIFT                     (18U)           /* Shift value for the SYNCH field */
#define FLEXCAN_ESR1_SYNCH(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_SYNCH_SHIFT)) & FLEXCAN_ESR1_SYNCH_MASK) /* Constructs the SYNCH field value */
/*
 *  This bit indicates the synchronization status.
 */
#define FLEXCAN_ESR1_BOFFDONEINT_MASK                (0x80000U)      /* Mask for the BOFFDONEINT field */
#define FLEXCAN_ESR1_BOFFDONEINT_SHIFT               (19U)           /* Shift value for the BOFFDONEINT field */
#define FLEXCAN_ESR1_BOFFDONEINT(x)                  (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)) & FLEXCAN_ESR1_BOFFDONEINT_MASK) /* Constructs the BOFFDONEINT field value */
/*
 *  This bit indicates a bus off done interrupt.
 */
#define FLEXCAN_ESR1_ERRINT_FAST_MASK                (0x100000U)     /* Mask for the ERRINT_FAST field */
#define FLEXCAN_ESR1_ERRINT_FAST_SHIFT               (20U)           /* Shift value for the ERRINT_FAST field */
#define FLEXCAN_ESR1_ERRINT_FAST(x)                  (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_ERRINT_FAST_SHIFT)) & FLEXCAN_ESR1_ERRINT_FAST_MASK) /* Constructs the ERRINT_FAST field value */
/*
 *  This bit indicates a fast error interrupt.
 */
#define FLEXCAN_ESR1_ERROVR_MASK                     (0x200000U)     /* Mask for the ERROVR field */
#define FLEXCAN_ESR1_ERROVR_SHIFT                    (21U)           /* Shift value for the ERROVR field */
#define FLEXCAN_ESR1_ERROVR(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ESR1_ERROVR_SHIFT)) & FLEXCAN_ESR1_ERROVR_MASK) /* Constructs the ERROVR field value */
/*
 *  This bit indicates an error overrun.
 */



#define FLEXCAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)   /* Mask for the BUF31TO0M field */
#define FLEXCAN_IMASK1_BUF31TO0M_SHIFT               (0U)            /* Shift value for the BUF31TO0M field */
#define FLEXCAN_IMASK1_BUF31TO0M(x)                  (((uint32)(((uint32)(x)) << FLEXCAN_IMASK1_BUF31TO0M_SHIFT)) & FLEXCAN_IMASK1_BUF31TO0M_MASK) /* Constructs the BUF31TO0M field value */
/*
 *  This field masks interrupts for buffers 0 to 31.
 */



#define FLEXCAN_IFLAG1_BUF0I_MASK                    (0x1U)          /* Mask for the BUF0I field */
#define FLEXCAN_IFLAG1_BUF0I_SHIFT                   (0U)            /* Shift value for the BUF0I field */
#define FLEXCAN_IFLAG1_BUF0I(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF0I_SHIFT)) & FLEXCAN_IFLAG1_BUF0I_MASK) /* Constructs the BUF0I field value */
/*
 *  This bit indicates an interrupt for buffer 0.
 */
#define FLEXCAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)         /* Mask for the BUF4TO1I field */
#define FLEXCAN_IFLAG1_BUF4TO1I_SHIFT                (1U)            /* Shift value for the BUF4TO1I field */
#define FLEXCAN_IFLAG1_BUF4TO1I(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT)) & FLEXCAN_IFLAG1_BUF4TO1I_MASK) /* Constructs the BUF4TO1I field value */
/*
 *  These bits indicate interrupts for buffers 1 to 4.
 */
#define FLEXCAN_IFLAG1_BUF5I_MASK                    (0x20U)         /* Mask for the BUF5I field */
#define FLEXCAN_IFLAG1_BUF5I_SHIFT                   (5U)            /* Shift value for the BUF5I field */
#define FLEXCAN_IFLAG1_BUF5I(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF5I_SHIFT)) & FLEXCAN_IFLAG1_BUF5I_MASK) /* Constructs the BUF5I field value */
/*
 *  This bit indicates an interrupt for buffer 5.
 */
#define FLEXCAN_IFLAG1_BUF6I_MASK                    (0x40U)         /* Mask for the BUF6I field */
#define FLEXCAN_IFLAG1_BUF6I_SHIFT                   (6U)            /* Shift value for the BUF6I field */
#define FLEXCAN_IFLAG1_BUF6I(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF6I_SHIFT)) & FLEXCAN_IFLAG1_BUF6I_MASK) /* Constructs the BUF6I field value */
/*
 *  This bit indicates an interrupt for buffer 6.
 */
#define FLEXCAN_IFLAG1_BUF7I_MASK                    (0x80U)         /* Mask for the BUF7I field */
#define FLEXCAN_IFLAG1_BUF7I_SHIFT                   (7U)            /* Shift value for the BUF7I field */
#define FLEXCAN_IFLAG1_BUF7I(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF7I_SHIFT)) & FLEXCAN_IFLAG1_BUF7I_MASK) /* Constructs the BUF7I field value */
/*
 *  This bit indicates an interrupt for buffer 7.
 */
#define FLEXCAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)   /* Mask for the BUF31TO8I field */
#define FLEXCAN_IFLAG1_BUF31TO8I_SHIFT               (8U)            /* Shift value for the BUF31TO8I field */
#define FLEXCAN_IFLAG1_BUF31TO8I(x)                  (((uint32)(((uint32)(x)) << FLEXCAN_IFLAG1_BUF31TO8I_SHIFT)) & FLEXCAN_IFLAG1_BUF31TO8I_MASK) /* Constructs the BUF31TO8I field value */
/*
 *  These bits indicate interrupts for buffers 8 to 31.
 */



#define FLEXCAN_CTRL2_EDFLTDIS_MASK                  (0x800U)        /* Mask for the EDFLTDIS field */
#define FLEXCAN_CTRL2_EDFLTDIS_SHIFT                 (11U)           /* Shift value for the EDFLTDIS field */
#define FLEXCAN_CTRL2_EDFLTDIS(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK) /* Constructs the EDFLTDIS field value */
/*
 *  This bit disables the edge filter.
 */
#define FLEXCAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)       /* Mask for the ISOCANFDEN field */
#define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT               (12U)           /* Shift value for the ISOCANFDEN field */
#define FLEXCAN_CTRL2_ISOCANFDEN(x)                  (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT)) & FLEXCAN_CTRL2_ISOCANFDEN_MASK) /* Constructs the ISOCANFDEN field value */
/*
 *  This bit enables or disables the ISO CAN FD feature.
 */
#define FLEXCAN_CTRL2_BTE_MASK                       (0x2000U)       /* Mask for the BTE field */
#define FLEXCAN_CTRL2_BTE_SHIFT                      (13U)           /* Shift value for the BTE field */
#define FLEXCAN_CTRL2_BTE(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_BTE_SHIFT)) & FLEXCAN_CTRL2_BTE_MASK) /* Constructs the BTE field value */
/*
 *  This bit enables or disables the bit timing extension.
 */
#define FLEXCAN_CTRL2_PREXCEN_MASK                   (0x4000U)       /* Mask for the PREXCEN field */
#define FLEXCAN_CTRL2_PREXCEN_SHIFT                  (14U)           /* Shift value for the PREXCEN field */
#define FLEXCAN_CTRL2_PREXCEN(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_PREXCEN_SHIFT)) & FLEXCAN_CTRL2_PREXCEN_MASK) /* Constructs the PREXCEN field value */
/*
 *  This bit enables or disables the protocol exception feature.
 */
#define FLEXCAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)       /* Mask for the TIMER_SRC field */
#define FLEXCAN_CTRL2_TIMER_SRC_SHIFT                (15U)           /* Shift value for the TIMER_SRC field */
#define FLEXCAN_CTRL2_TIMER_SRC(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_TIMER_SRC_SHIFT)) & FLEXCAN_CTRL2_TIMER_SRC_MASK) /* Constructs the TIMER_SRC field value */
/*
 *  This bit selects the source for the timer.
 */
#define FLEXCAN_CTRL2_EACEN_MASK                     (0x10000U)      /* Mask for the EACEN field */
#define FLEXCAN_CTRL2_EACEN_SHIFT                    (16U)           /* Shift value for the EACEN field */
#define FLEXCAN_CTRL2_EACEN(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK) /* Constructs the EACEN field value */
/*
 *  This bit enables or disables the entire frame arbitration field comparison.
 */
#define FLEXCAN_CTRL2_RRS_MASK                       (0x20000U)      /* Mask for the RRS field */
#define FLEXCAN_CTRL2_RRS_SHIFT                      (17U)           /* Shift value for the RRS field */
#define FLEXCAN_CTRL2_RRS(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK) /* Constructs the RRS field value */
/*
 *  This bit configures the remote request storing behavior.
 */
#define FLEXCAN_CTRL2_MRP_MASK                       (0x40000U)      /* Mask for the MRP field */
#define FLEXCAN_CTRL2_MRP_SHIFT                      (18U)           /* Shift value for the MRP field */
#define FLEXCAN_CTRL2_MRP(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK) /* Constructs the MRP field value */
/*
 *  This bit sets the priority for mailbox reception.
 */
#define FLEXCAN_CTRL2_TASD_MASK                      (0xF80000U)     /* Mask for the TASD field */
#define FLEXCAN_CTRL2_TASD_SHIFT                     (19U)           /* Shift value for the TASD field */
#define FLEXCAN_CTRL2_TASD(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK) /* Constructs the TASD field value */
/*
 *  This field defines the Tx arbitration start delay.
 */
#define FLEXCAN_CTRL2_RFFN_MASK                      (0xF000000U)    /* Mask for the RFFN field */
#define FLEXCAN_CTRL2_RFFN_SHIFT                     (24U)           /* Shift value for the RFFN field */
#define FLEXCAN_CTRL2_RFFN(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_RFFN_SHIFT)) & FLEXCAN_CTRL2_RFFN_MASK) /* Constructs the RFFN field value */
/*
 *  This field defines the number of Rx FIFO filters.
 */
#define FLEXCAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)   /* Mask for the WRMFRZ field */
#define FLEXCAN_CTRL2_WRMFRZ_SHIFT                   (28U)           /* Shift value for the WRMFRZ field */
#define FLEXCAN_CTRL2_WRMFRZ(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_WRMFRZ_SHIFT)) & FLEXCAN_CTRL2_WRMFRZ_MASK) /* Constructs the WRMFRZ field value */
/*
 *  This bit enables write access in freeze mode.
 */
#define FLEXCAN_CTRL2_ECRWRE_MASK                    (0x20000000U)   /* Mask for the ECRWRE field */
#define FLEXCAN_CTRL2_ECRWRE_SHIFT                   (29U)           /* Shift value for the ECRWRE field */
#define FLEXCAN_CTRL2_ECRWRE(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_ECRWRE_SHIFT)) & FLEXCAN_CTRL2_ECRWRE_MASK) /* Constructs the ECRWRE field value */
/*
 *  This bit enables write access to the error correction register.
 */
#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)   /* Mask for the BOFFDONEINT field */
#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)           /* Shift value for the BOFFDONEINT field */
#define FLEXCAN_CTRL2_BOFFDONEMSK(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK) /* Constructs the BOFFDONEINT field value */
/*
 *  This bit masks the bus off done interrupt.
 */
#define FLEXCAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)   /* Mask for the ERRMSK_FAST field */
#define FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)           /* Shift value for the ERRMSK_FAST field */
#define FLEXCAN_CTRL2_ERRMSK_FAST(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT)) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK) /* Constructs the ERRMSK_FAST field value */
/*
 *  This bit masks the fast error interrupt.
 */



#define FLEXCAN_ESR2_IMB_MASK                        (0x2000U)       /* Mask for the IMB field */
#define FLEXCAN_ESR2_IMB_SHIFT                       (13U)           /* Shift value for the IMB field */
#define FLEXCAN_ESR2_IMB(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_ESR2_IMB_SHIFT)) & FLEXCAN_ESR2_IMB_MASK) /* Constructs the IMB field value */
/*
 *  This bit indicates an inactive mailbox.
 */
#define FLEXCAN_ESR2_VPS_MASK                        (0x4000U)       /* Mask for the VPS field */
#define FLEXCAN_ESR2_VPS_SHIFT                       (14U)           /* Shift value for the VPS field */
#define FLEXCAN_ESR2_VPS(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_ESR2_VPS_SHIFT)) & FLEXCAN_ESR2_VPS_MASK) /* Constructs the VPS field value */
/*
 *  This bit indicates the valid priority status.
 */
#define FLEXCAN_ESR2_LPTM_MASK                       (0x7F0000U)     /* Mask for the LPTM field */
#define FLEXCAN_ESR2_LPTM_SHIFT                      (16U)           /* Shift value for the LPTM field */
#define FLEXCAN_ESR2_LPTM(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_ESR2_LPTM_SHIFT)) & FLEXCAN_ESR2_LPTM_MASK) /* Constructs the LPTM field value */
/*
 *  This field indicates the lowest priority Tx mailbox.
 */



#define FLEXCAN_CRCR_TXCRC_MASK                      (0x7FFFU)       /* Mask for the TXCRC field */
#define FLEXCAN_CRCR_TXCRC_SHIFT                     (0U)            /* Shift value for the TXCRC field */
#define FLEXCAN_CRCR_TXCRC(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CRCR_TXCRC_SHIFT)) & FLEXCAN_CRCR_TXCRC_MASK) /* Constructs the TXCRC field value */
/*
 *  This field holds the transmitted CRC value.
 */
#define FLEXCAN_CRCR_MBCRC_MASK                      (0x7F0000U)     /* Mask for the MBCRC field */
#define FLEXCAN_CRCR_MBCRC_SHIFT                     (16U)           /* Shift value for the MBCRC field */
#define FLEXCAN_CRCR_MBCRC(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CRCR_MBCRC_SHIFT)) & FLEXCAN_CRCR_MBCRC_MASK) /* Constructs the MBCRC field value */
/*
 *  This field holds the CRC value for the mailbox.
 */



#define FLEXCAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)   /* Mask for the FGM field */
#define FLEXCAN_RXFGMASK_FGM_SHIFT                   (0U)            /* Shift value for the FGM field */
#define FLEXCAN_RXFGMASK_FGM(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_RXFGMASK_FGM_SHIFT)) & FLEXCAN_RXFGMASK_FGM_MASK) /* Constructs the FGM field value */
/*
 *  This register defines the global mask for the Rx FIFO.
 */



#define FLEXCAN_RXFIR_IDHIT_MASK                     (0x1FFU)        /* Mask for the IDHIT field */
#define FLEXCAN_RXFIR_IDHIT_SHIFT                    (0U)            /* Shift value for the IDHIT field */
#define FLEXCAN_RXFIR_IDHIT(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_RXFIR_IDHIT_SHIFT)) & FLEXCAN_RXFIR_IDHIT_MASK) /* Constructs the IDHIT field value */
/*
 *  This field indicates which filter was hit by the received message.
 */



#define FLEXCAN_CBT_EPSEG2_MASK                      (0x1FU)         /* Mask for the EPSEG2 field */
#define FLEXCAN_CBT_EPSEG2_SHIFT                     (0U)            /* Shift value for the EPSEG2 field */
#define FLEXCAN_CBT_EPSEG2(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CBT_EPSEG2_SHIFT)) & FLEXCAN_CBT_EPSEG2_MASK) /* Constructs the EPSEG2 field value */
/*
 *  This field defines the extended phase segment 2 for bit timing.
 */
#define FLEXCAN_CBT_EPSEG1_MASK                      (0x3E0U)        /* Mask for the EPSEG1 field */
#define FLEXCAN_CBT_EPSEG1_SHIFT                     (5U)            /* Shift value for the EPSEG1 field */
#define FLEXCAN_CBT_EPSEG1(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_CBT_EPSEG1_SHIFT)) & FLEXCAN_CBT_EPSEG1_MASK) /* Constructs the EPSEG1 field value */
/*
 *  This field defines the extended phase segment 1 for bit timing.
 */
#define FLEXCAN_CBT_EPROPSEG_MASK                    (0xFC00U)       /* Mask for the EPROPSEG field */
#define FLEXCAN_CBT_EPROPSEG_SHIFT                   (10U)           /* Shift value for the EPROPSEG field */
#define FLEXCAN_CBT_EPROPSEG(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_CBT_EPROPSEG_SHIFT)) & FLEXCAN_CBT_EPROPSEG_MASK) /* Constructs the EPROPSEG field value */
/*
 *  This field defines the extended propagation segment for bit timing.
 */
#define FLEXCAN_CBT_ERJW_MASK                        (0xF0000U)      /* Mask for the ERJW field */
#define FLEXCAN_CBT_ERJW_SHIFT                       (16U)           /* Shift value for the ERJW field */
#define FLEXCAN_CBT_ERJW(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_CBT_ERJW_SHIFT)) & FLEXCAN_CBT_ERJW_MASK) /* Constructs the ERJW field value */
/*
 *  This field defines the extended resynchronization jump width.
 */
#define FLEXCAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)   /* Mask for the EPRESDIV field */
#define FLEXCAN_CBT_EPRESDIV_SHIFT                   (21U)           /* Shift value for the EPRESDIV field */
#define FLEXCAN_CBT_EPRESDIV(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_CBT_EPRESDIV_SHIFT)) & FLEXCAN_CBT_EPRESDIV_MASK) /* Constructs the EPRESDIV field value */
/*
 *  This field defines the extended prescaler division factor.
 */
#define FLEXCAN_CBT_BTF_MASK                         (0x80000000U)   /* Mask for the BTF field */
#define FLEXCAN_CBT_BTF_SHIFT                        (31U)           /* Shift value for the BTF field */
#define FLEXCAN_CBT_BTF(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_CBT_BTF_SHIFT)) & FLEXCAN_CBT_BTF_MASK) /* Constructs the BTF field value */
/*
 *  This bit selects the bit timing format.
 */



#define FLEXCAN_MECR_NCEFAFRZ_MASK                   (0x80U)         /* Mask for the NCEFAFRZ field */
#define FLEXCAN_MECR_NCEFAFRZ_SHIFT                  (7U)            /* Shift value for the NCEFAFRZ field */
#define FLEXCAN_MECR_NCEFAFRZ(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_MECR_NCEFAFRZ_SHIFT)) & FLEXCAN_MECR_NCEFAFRZ_MASK) /* Constructs the NCEFAFRZ field value */
/*
 *  This bit configures the behavior for non-correctable errors.
 */
#define FLEXCAN_MECR_ECCDIS_MASK                     (0x100U)        /* Mask for the ECCDIS field */
#define FLEXCAN_MECR_ECCDIS_SHIFT                    (8U)            /* Shift value for the ECCDIS field */
#define FLEXCAN_MECR_ECCDIS(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_MECR_ECCDIS_SHIFT)) & FLEXCAN_MECR_ECCDIS_MASK) /* Constructs the ECCDIS field value */
/*
 *  This bit disables error correction.
 */
#define FLEXCAN_MECR_RERRDIS_MASK                    (0x200U)        /* Mask for the RERRDIS field */
#define FLEXCAN_MECR_RERRDIS_SHIFT                   (9U)            /* Shift value for the RERRDIS field */
#define FLEXCAN_MECR_RERRDIS(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_MECR_RERRDIS_SHIFT)) & FLEXCAN_MECR_RERRDIS_MASK) /* Constructs the RERRDIS field value */
/*
 *  This bit disables RAM error detection.
 */
#define FLEXCAN_MECR_EXTERRIE_MASK                   (0x2000U)       /* Mask for the EXTERRIE field */
#define FLEXCAN_MECR_EXTERRIE_SHIFT                  (13U)           /* Shift value for the EXTERRIE field */
#define FLEXCAN_MECR_EXTERRIE(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_MECR_EXTERRIE_SHIFT)) & FLEXCAN_MECR_EXTERRIE_MASK) /* Constructs the EXTERRIE field value */
/*
 *  This bit enables extended error injection.
 */
#define FLEXCAN_MECR_FAERRIE_MASK                    (0x4000U)       /* Mask for the FAERRIE field */
#define FLEXCAN_MECR_FAERRIE_SHIFT                   (14U)           /* Shift value for the FAERRIE field */
#define FLEXCAN_MECR_FAERRIE(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_MECR_FAERRIE_SHIFT)) & FLEXCAN_MECR_FAERRIE_MASK) /* Constructs the FAERRIE field value */
/*
 *  This bit enables FlexCAN access error injection.
 */
#define FLEXCAN_MECR_HAERRIE_MASK                    (0x8000U)       /* Mask for the HAERRIE field */
#define FLEXCAN_MECR_HAERRIE_SHIFT                   (15U)           /* Shift value for the HAERRIE field */
#define FLEXCAN_MECR_HAERRIE(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_MECR_HAERRIE_SHIFT)) & FLEXCAN_MECR_HAERRIE_MASK) /* Constructs the HAERRIE field value */
/*
 *  This bit enables host access error injection.
 */
#define FLEXCAN_MECR_CEI_MSK_MASK                    (0x10000U)      /* Mask for the CEI_MSK field */
#define FLEXCAN_MECR_CEI_MSK_SHIFT                   (16U)           /* Shift value for the CEI_MSK field */
#define FLEXCAN_MECR_CEI_MSK(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_MECR_CEI_MSK_SHIFT)) & FLEXCAN_MECR_CEI_MSK_MASK) /* Constructs the CEI_MSK field value */
/*
 *  This bit masks the correctable error interrupt.
 */
#define FLEXCAN_MECR_FANCEI_MSK_MASK                 (0x40000U)      /* Mask for the FANCEI_MSK field */
#define FLEXCAN_MECR_FANCEI_MSK_SHIFT                (18U)           /* Shift value for the FANCEI_MSK field */
#define FLEXCAN_MECR_FANCEI_MSK(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_MECR_FANCEI_MSK_SHIFT)) & FLEXCAN_MECR_FANCEI_MSK_MASK) /* Constructs the FANCEI_MSK field value */
/*
 *  This bit masks the FlexCAN access non-correctable error interrupt.
 */
#define FLEXCAN_MECR_HANCEI_MSK_MASK                 (0x80000U)      /* Mask for the HANCEI_MSK field */
#define FLEXCAN_MECR_HANCEI_MSK_SHIFT                (19U)           /* Shift value for the HANCEI_MSK field */
#define FLEXCAN_MECR_HANCEI_MSK(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_MECR_HANCEI_MSK_SHIFT)) & FLEXCAN_MECR_HANCEI_MSK_MASK) /* Constructs the HANCEI_MSK field value */
/*
 *  This bit masks the host access non-correctable error interrupt.
 */
#define FLEXCAN_MECR_ECRWRDIS_MASK                   (0x80000000U)   /* Mask for the ECRWRDIS field */
#define FLEXCAN_MECR_ECRWRDIS_SHIFT                  (31U)           /* Shift value for the ECRWRDIS field */
#define FLEXCAN_MECR_ECRWRDIS(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_MECR_ECRWRDIS_SHIFT)) & FLEXCAN_MECR_ECRWRDIS_MASK) /* Constructs the ECRWRDIS field value */
/*
 *  This bit disables write access to the error configuration register.
 */



#define FLEXCAN_CS_TIME_STAMP_MASK                   (0xFFFFU)       /* Mask for the TIME_STAMP field */
#define FLEXCAN_CS_TIME_STAMP_SHIFT                  (0U)            /* Shift value for the TIME_STAMP field */
#define FLEXCAN_CS_TIME_STAMP(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_CS_TIME_STAMP_SHIFT)) & FLEXCAN_CS_TIME_STAMP_MASK) /* Constructs the TIME_STAMP field value */
/*
 *  This field holds the time stamp of the message.
 */
#define FLEXCAN_CS_DLC_MASK                          (0xF0000U)      /* Mask for the DLC field */
#define FLEXCAN_CS_DLC_SHIFT                         (16U)           /* Shift value for the DLC field */
#define FLEXCAN_CS_DLC(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_DLC_SHIFT)) & FLEXCAN_CS_DLC_MASK) /* Constructs the DLC field value */
/*
 *  This field defines the data length code of the message.
 */
#define FLEXCAN_CS_RTR_MASK                          (0x100000U)     /* Mask for the RTR field */
#define FLEXCAN_CS_RTR_SHIFT                         (20U)           /* Shift value for the RTR field */
#define FLEXCAN_CS_RTR(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_RTR_SHIFT)) & FLEXCAN_CS_RTR_MASK) /* Constructs the RTR field value */
/*
 *  This bit indicates a remote transmission request.
 */
#define FLEXCAN_CS_IDE_MASK                          (0x200000U)     /* Mask for the IDE field */
#define FLEXCAN_CS_IDE_SHIFT                         (21U)           /* Shift value for the IDE field */
#define FLEXCAN_CS_IDE(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_IDE_SHIFT)) & FLEXCAN_CS_IDE_MASK) /* Constructs the IDE field value */
/*
 *  This bit indicates an extended identifier.
 */
#define FLEXCAN_CS_SRR_MASK                          (0x400000U)     /* Mask for the SRR field */
#define FLEXCAN_CS_SRR_SHIFT                         (22U)           /* Shift value for the SRR field */
#define FLEXCAN_CS_SRR(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_SRR_SHIFT)) & FLEXCAN_CS_SRR_MASK) /* Constructs the SRR field value */
/*
 *  This bit is used for substitute remote request.
 */
#define FLEXCAN_CS_CODE_MASK                         (0xF000000U)    /* Mask for the CODE field */
#define FLEXCAN_CS_CODE_SHIFT                        (24U)           /* Shift value for the CODE field */
#define FLEXCAN_CS_CODE(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_CS_CODE_SHIFT)) & FLEXCAN_CS_CODE_MASK) /* Constructs the CODE field value */
/*
 *  This field defines the code of the message buffer.
 */
#define FLEXCAN_CS_ESI_MASK                          (0x20000000U)   /* Mask for the ESI field */
#define FLEXCAN_CS_ESI_SHIFT                         (29U)           /* Shift value for the ESI field */
#define FLEXCAN_CS_ESI(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_ESI_SHIFT)) & FLEXCAN_CS_ESI_MASK) /* Constructs the ESI field value */
/*
 *  This bit indicates the error state.
 */
#define FLEXCAN_CS_BRS_MASK                          (0x40000000U)   /* Mask for the BRS field */
#define FLEXCAN_CS_BRS_SHIFT                         (30U)           /* Shift value for the BRS field */
#define FLEXCAN_CS_BRS(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_BRS_SHIFT)) & FLEXCAN_CS_BRS_MASK) /* Constructs the BRS field value */
/*
 *  This bit indicates a bit rate switch.
 */
#define FLEXCAN_CS_EDL_MASK                          (0x80000000U)   /* Mask for the EDL field */
#define FLEXCAN_CS_EDL_SHIFT                         (31U)           /* Shift value for the EDL field */
#define FLEXCAN_CS_EDL(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_CS_EDL_SHIFT)) & FLEXCAN_CS_EDL_MASK) /* Constructs the EDL field value */
/*
 *  This bit indicates an extended data length.
 */
/* The count of CAN_CS */
#define FLEXCAN_CS_COUNT                             (128U)          /* Number of message buffer CS registers */



#define FLEXCAN_ID_EXT_MASK                          (0x3FFFFU)      /* Mask for the EXT field */
#define FLEXCAN_ID_EXT_SHIFT                         (0U)            /* Shift value for the EXT field */
#define FLEXCAN_ID_EXT(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_ID_EXT_SHIFT)) & FLEXCAN_ID_EXT_MASK) /* Constructs the EXT field value */
/*
 *  This field holds the extended identifier.
 */
#define FLEXCAN_ID_STD_MASK                          (0x1FFC0000U)   /* Mask for the STD field */
#define FLEXCAN_ID_STD_SHIFT                         (18U)           /* Shift value for the STD field */
#define FLEXCAN_ID_STD(x)                            (((uint32)(((uint32)(x)) << FLEXCAN_ID_STD_SHIFT)) & FLEXCAN_ID_STD_MASK) /* Constructs the STD field value */
/*
 *  This field holds the standard identifier.
 */
#define FLEXCAN_ID_PRIO_MASK                         (0xE0000000U)   /* Mask for the PRIO field */
#define FLEXCAN_ID_PRIO_SHIFT                        (29U)           /* Shift value for the PRIO field */
#define FLEXCAN_ID_PRIO(x)                           (((uint32)(((uint32)(x)) << FLEXCAN_ID_PRIO_SHIFT)) & FLEXCAN_ID_PRIO_MASK) /* Constructs the PRIO field value */
/*
 *  This field defines the priority of the message.
 */
/* The count of CAN_ID */
#define FLEXCAN_ID_COUNT                             (128U)          /* Number of message buffer ID registers */



#define FLEXCAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)         /* Mask for the DATA_BYTE_3 field */
#define FLEXCAN_WORD0_DATA_BYTE_3_SHIFT              (0U)            /* Shift value for the DATA_BYTE_3 field */
#define FLEXCAN_WORD0_DATA_BYTE_3(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD0_DATA_BYTE_3_SHIFT)) & FLEXCAN_WORD0_DATA_BYTE_3_MASK) /* Constructs the DATA_BYTE_3 field value */
/*
 *  This field holds data byte 3 of the message.
 */
#define FLEXCAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)       /* Mask for the DATA_BYTE_2 field */
#define FLEXCAN_WORD0_DATA_BYTE_2_SHIFT              (8U)            /* Shift value for the DATA_BYTE_2 field */
#define FLEXCAN_WORD0_DATA_BYTE_2(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD0_DATA_BYTE_2_SHIFT)) & FLEXCAN_WORD0_DATA_BYTE_2_MASK) /* Constructs the DATA_BYTE_2 field value */
/*
 *  This field holds data byte 2 of the message.
 */
#define FLEXCAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)     /* Mask for the DATA_BYTE_1 field */
#define FLEXCAN_WORD0_DATA_BYTE_1_SHIFT              (16U)           /* Shift value for the DATA_BYTE_1 field */
#define FLEXCAN_WORD0_DATA_BYTE_1(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD0_DATA_BYTE_1_SHIFT)) & FLEXCAN_WORD0_DATA_BYTE_1_MASK) /* Constructs the DATA_BYTE_1 field value */
/*
 *  This field holds data byte 1 of the message.
 */
#define FLEXCAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)   /* Mask for the DATA_BYTE_0 field */
#define FLEXCAN_WORD0_DATA_BYTE_0_SHIFT              (24U)           /* Shift value for the DATA_BYTE_0 field */
#define FLEXCAN_WORD0_DATA_BYTE_0(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD0_DATA_BYTE_0_SHIFT)) & FLEXCAN_WORD0_DATA_BYTE_0_MASK) /* Constructs the DATA_BYTE_0 field value */
/*
 *  This field holds data byte 0 of the message.
 */
/* The count of CAN_WORD0 */
#define FLEXCAN_WORD0_COUNT                          (128U)          /* Number of message buffer WORD0 registers */



#define FLEXCAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)         /* Mask for the DATA_BYTE_7 field */
#define FLEXCAN_WORD1_DATA_BYTE_7_SHIFT              (0U)            /* Shift value for the DATA_BYTE_7 field */
#define FLEXCAN_WORD1_DATA_BYTE_7(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD1_DATA_BYTE_7_SHIFT)) & FLEXCAN_WORD1_DATA_BYTE_7_MASK) /* Constructs the DATA_BYTE_7 field value */
/*
 *  This field holds data byte 7 of the message.
 */
#define FLEXCAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)       /* Mask for the DATA_BYTE_6 field */
#define FLEXCAN_WORD1_DATA_BYTE_6_SHIFT              (8U)            /* Shift value for the DATA_BYTE_6 field */
#define FLEXCAN_WORD1_DATA_BYTE_6(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD1_DATA_BYTE_6_SHIFT)) & FLEXCAN_WORD1_DATA_BYTE_6_MASK) /* Constructs the DATA_BYTE_6 field value */
/*
 *  This field holds data byte 6 of the message.
 */
#define FLEXCAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)     /* Mask for the DATA_BYTE_5 field */
#define FLEXCAN_WORD1_DATA_BYTE_5_SHIFT              (16U)           /* Shift value for the DATA_BYTE_5 field */
#define FLEXCAN_WORD1_DATA_BYTE_5(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD1_DATA_BYTE_5_SHIFT)) & FLEXCAN_WORD1_DATA_BYTE_5_MASK) /* Constructs the DATA_BYTE_5 field value */
/*
 *  This field holds data byte 5 of the message.
 */
#define FLEXCAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)   /* Mask for the DATA_BYTE_4 field */
#define FLEXCAN_WORD1_DATA_BYTE_4_SHIFT              (24U)           /* Shift value for the DATA_BYTE_4 field */
#define FLEXCAN_WORD1_DATA_BYTE_4(x)                 (((uint32)(((uint32)(x)) << FLEXCAN_WORD1_DATA_BYTE_4_SHIFT)) & FLEXCAN_WORD1_DATA_BYTE_4_MASK) /* Constructs the DATA_BYTE_4 field value */
/*
 *  This field holds data byte 4 of the message.
 */
/* The count of CAN_WORD1 */
#define FLEXCAN_WORD1_COUNT                          (128U)          /* Number of message buffer WORD1 registers */



#define FLEXCAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)   /* Mask for the MI field */
#define FLEXCAN_RXIMR_MI_SHIFT                       (0U)            /* Shift value for the MI field */
#define FLEXCAN_RXIMR_MI(x)                          (((uint32)(((uint32)(x)) << FLEXCAN_RXIMR_MI_SHIFT)) & FLEXCAN_RXIMR_MI_MASK) /* Constructs the MI field value */
/*
 *  This register defines the individual mask for Rx mailboxes.
 */
/* The count of CAN_RXIMR */
#define FLEXCAN_RXIMR_COUNT                          (128U)          /* Number of Rx individual mask registers */



#define FLEXCAN_FDCTRL_TDCVAL_MASK                   (0x3FU)         /* Mask for the TDCVAL field */
#define FLEXCAN_FDCTRL_TDCVAL_SHIFT                  (0U)            /* Shift value for the TDCVAL field */
#define FLEXCAN_FDCTRL_TDCVAL(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_TDCVAL_SHIFT)) & FLEXCAN_FDCTRL_TDCVAL_MASK) /* Constructs the TDCVAL field value */
/*
 *  This field holds the transceiver delay compensation value.
 */
#define FLEXCAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)       /* Mask for the TDCOFF field */
#define FLEXCAN_FDCTRL_TDCOFF_SHIFT                  (8U)            /* Shift value for the TDCOFF field */
#define FLEXCAN_FDCTRL_TDCOFF(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_TDCOFF_SHIFT)) & FLEXCAN_FDCTRL_TDCOFF_MASK) /* Constructs the TDCOFF field value */
/*
 *  This field defines the transceiver delay compensation offset.
 */
#define FLEXCAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)       /* Mask for the TDCFAIL field */
#define FLEXCAN_FDCTRL_TDCFAIL_SHIFT                 (14U)           /* Shift value for the TDCFAIL field */
#define FLEXCAN_FDCTRL_TDCFAIL(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK) /* Constructs the TDCFAIL field value */
/*
 *  This bit indicates a transceiver delay compensation failure.
 */
#define FLEXCAN_FDCTRL_TDCEN_MASK                    (0x8000U)       /* Mask for the TDCEN field */
#define FLEXCAN_FDCTRL_TDCEN_SHIFT                   (15U)           /* Shift value for the TDCEN field */
#define FLEXCAN_FDCTRL_TDCEN(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_TDCEN_SHIFT)) & FLEXCAN_FDCTRL_TDCEN_MASK) /* Constructs the TDCEN field value */
/*
 *  This bit enables or disables transceiver delay compensation.
 */
#define FLEXCAN_FDCTRL_MBDSR0_MASK                   (0x30000U)      /* Mask for the MBDSR0 field */
#define FLEXCAN_FDCTRL_MBDSR0_SHIFT                  (16U)           /* Shift value for the MBDSR0 field */
#define FLEXCAN_FDCTRL_MBDSR0(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_MBDSR0_SHIFT)) & FLEXCAN_FDCTRL_MBDSR0_MASK) /* Constructs the MBDSR0 field value */
/*
 *  This field defines the message buffer data size for region 0.
 */
#define FLEXCAN_FDCTRL_MBDSR1_MASK                   (0x180000U)     /* Mask for the MBDSR1 field */
#define FLEXCAN_FDCTRL_MBDSR1_SHIFT                  (19U)           /* Shift value for the MBDSR1 field */
#define FLEXCAN_FDCTRL_MBDSR1(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_MBDSR1_SHIFT)) & FLEXCAN_FDCTRL_MBDSR1_MASK) /* Constructs the MBDSR1 field value */
/*
 *  This field defines the message buffer data size for region 1.
 */
#define FLEXCAN_FDCTRL_MBDSR2_MASK                   (0xC00000U)     /* Mask for the MBDSR2 field */
#define FLEXCAN_FDCTRL_MBDSR2_SHIFT                  (22U)           /* Shift value for the MBDSR2 field */
#define FLEXCAN_FDCTRL_MBDSR2(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_MBDSR2_SHIFT)) & FLEXCAN_FDCTRL_MBDSR2_MASK) /* Constructs the MBDSR2 field value */
/*
 *  This field defines the message buffer data size for region 2.
 */
#define FLEXCAN_FDCTRL_MBDSR3_MASK                   (0x6000000U)    /* Mask for the MBDSR3 field */
#define FLEXCAN_FDCTRL_MBDSR3_SHIFT                  (25U)           /* Shift value for the MBDSR3 field */
#define FLEXCAN_FDCTRL_MBDSR3(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_MBDSR3_SHIFT)) & FLEXCAN_FDCTRL_MBDSR3_MASK) /* Constructs the MBDSR3 field value */
/*
 *  This field defines the message buffer data size for region 3.
 */
#define FLEXCAN_FDCTRL_FDRATE_MASK                   (0x80000000U)   /* Mask for the FDRATE field */
#define FLEXCAN_FDCTRL_FDRATE_SHIFT                  (31U)           /* Shift value for the FDRATE field */
#define FLEXCAN_FDCTRL_FDRATE(x)                     (((uint32)(((uint32)(x)) << FLEXCAN_FDCTRL_FDRATE_SHIFT)) & FLEXCAN_FDCTRL_FDRATE_MASK) /* Constructs the FDRATE field value */
/*
 *  This bit enables or disables the CAN FD rate.
 */



#define FLEXCAN_FDCBT_FPSEG2_MASK                    (7U)            /* Mask for the FPSEG2 field */
#define FLEXCAN_FDCBT_FPSEG2_SHIFT                   (0U)            /* Shift value for the FPSEG2 field */
#define FLEXCAN_FDCBT_FPSEG2(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_FDCBT_FPSEG2_SHIFT)) & FLEXCAN_FDCBT_FPSEG2_MASK) /* Constructs the FPSEG2 field value */
/*
 *  This field defines the fast phase segment 2 for CAN FD bit timing.
 */
#define FLEXCAN_FDCBT_FPSEG1_MASK                    (0xE0U)         /* Mask for the FPSEG1 field */
#define FLEXCAN_FDCBT_FPSEG1_SHIFT                   (5U)            /* Shift value for the FPSEG1 field */
#define FLEXCAN_FDCBT_FPSEG1(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_FDCBT_FPSEG1_SHIFT)) & FLEXCAN_FDCBT_FPSEG1_MASK) /* Constructs the FPSEG1 field value */
/*
 *  This field defines the fast phase segment 1 for CAN FD bit timing.
 */
#define FLEXCAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)       /* Mask for the FPROPSEG field */
#define FLEXCAN_FDCBT_FPROPSEG_SHIFT                 (10U)           /* Shift value for the FPROPSEG field */
#define FLEXCAN_FDCBT_FPROPSEG(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_FDCBT_FPROPSEG_SHIFT)) & FLEXCAN_FDCBT_FPROPSEG_MASK) /* Constructs the FPROPSEG field value */
/*
 *  This field defines the fast propagation segment for CAN FD bit timing.
 */
#define FLEXCAN_FDCBT_FRJW_MASK                      (0x70000U)      /* Mask for the FRJW field */
#define FLEXCAN_FDCBT_FRJW_SHIFT                     (16U)           /* Shift value for the FRJW field */
#define FLEXCAN_FDCBT_FRJW(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_FDCBT_FRJW_SHIFT)) & FLEXCAN_FDCBT_FRJW_MASK) /* Constructs the FRJW field value */
/*
 *  This field defines the fast resynchronization jump width for CAN FD.
 */
#define FLEXCAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)   /* Mask for the FPRESDIV field */
#define FLEXCAN_FDCBT_FPRESDIV_SHIFT                 (20U)           /* Shift value for the FPRESDIV field */
#define FLEXCAN_FDCBT_FPRESDIV(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_FDCBT_FPRESDIV_SHIFT)) & FLEXCAN_FDCBT_FPRESDIV_MASK) /* Constructs the FPRESDIV field value */
/*
 *  This field defines the fast prescaler division factor for CAN FD.
 */



#define FLEXCAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)        /* Mask for the ENPRESDIV field */
#define FLEXCAN_EPRS_ENPRESDIV_SHIFT                 (0U)            /* Shift value for the ENPRESDIV field */
#define FLEXCAN_EPRS_ENPRESDIV(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_EPRS_ENPRESDIV_SHIFT)) & FLEXCAN_EPRS_ENPRESDIV_MASK) /* Constructs the ENPRESDIV field value */
/*
 *  This field defines the enhanced nominal prescaler division factor.
 */
#define FLEXCAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)    /* Mask for the EDPRESDIV field */
#define FLEXCAN_EPRS_EDPRESDIV_SHIFT                 (16U)           /* Shift value for the EDPRESDIV field */
#define FLEXCAN_EPRS_EDPRESDIV(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_EPRS_EDPRESDIV_SHIFT)) & FLEXCAN_EPRS_EDPRESDIV_MASK) /* Constructs the EDPRESDIV field value */
/*
 *  This field defines the enhanced data phase prescaler division factor.
 */



#define FLEXCAN_ENCBT_NTSEG1_MASK                    (0xFFU)         /* Mask for the NTSEG1 field */
#define FLEXCAN_ENCBT_NTSEG1_SHIFT                   (0U)            /* Shift value for the NTSEG1 field */
#define FLEXCAN_ENCBT_NTSEG1(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ENCBT_NTSEG1_SHIFT)) & FLEXCAN_ENCBT_NTSEG1_MASK) /* Constructs the NTSEG1 field value */
/*
 *  This field defines the nominal time segment 1 for bit timing.
 */
#define FLEXCAN_ENCBT_NTSEG2_MASK                    (0x7F000U)      /* Mask for the NTSEG2 field */
#define FLEXCAN_ENCBT_NTSEG2_SHIFT                   (12U)           /* Shift value for the NTSEG2 field */
#define FLEXCAN_ENCBT_NTSEG2(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ENCBT_NTSEG2_SHIFT)) & FLEXCAN_ENCBT_NTSEG2_MASK) /* Constructs the NTSEG2 field value */
/*
 *  This field defines the nominal time segment 2 for bit timing.
 */
#define FLEXCAN_ENCBT_NRJW_MASK                      (0x1FC00000U)   /* Mask for the NRJW field */
#define FLEXCAN_ENCBT_NRJW_SHIFT                     (22U)           /* Shift value for the NRJW field */
#define FLEXCAN_ENCBT_NRJW(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ENCBT_NRJW_SHIFT)) & FLEXCAN_ENCBT_NRJW_MASK) /* Constructs the NRJW field value */
/*
 *  This field defines the nominal resynchronization jump width.
 */



#define FLEXCAN_EDCBT_DTSEG1_MASK                    (0x1FU)         /* Mask for the DTSEG1 field */
#define FLEXCAN_EDCBT_DTSEG1_SHIFT                   (0U)            /* Shift value for the DTSEG1 field */
#define FLEXCAN_EDCBT_DTSEG1(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_EDCBT_DTSEG1_SHIFT)) & FLEXCAN_EDCBT_DTSEG1_MASK) /* Constructs the DTSEG1 field value */
/*
 *  This field defines the data time segment 1 for bit timing.
 */
#define FLEXCAN_EDCBT_DTSEG2_MASK                    (0xF000U)       /* Mask for the DTSEG2 field */
#define FLEXCAN_EDCBT_DTSEG2_SHIFT                   (12U)           /* Shift value for the DTSEG2 field */
#define FLEXCAN_EDCBT_DTSEG2(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_EDCBT_DTSEG2_SHIFT)) & FLEXCAN_EDCBT_DTSEG2_MASK) /* Constructs the DTSEG2 field value */
/*
 *  This field defines the data time segment 2 for bit timing.
 */
#define FLEXCAN_EDCBT_DRJW_MASK                      (0x3C00000U)    /* Mask for the DRJW field */
#define FLEXCAN_EDCBT_DRJW_SHIFT                     (22U)           /* Shift value for the DRJW field */
#define FLEXCAN_EDCBT_DRJW(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_EDCBT_DRJW_SHIFT)) & FLEXCAN_EDCBT_DRJW_MASK) /* Constructs the DRJW field value */
/*
 *  This field defines the data resynchronization jump width.
 */



#define FLEXCAN_ETDC_ETDCVAL_MASK                    (0xFFU)         /* Mask for the ETDCVAL field */
#define FLEXCAN_ETDC_ETDCVAL_SHIFT                   (0U)            /* Shift value for the ETDCVAL field */
#define FLEXCAN_ETDC_ETDCVAL(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ETDC_ETDCVAL_SHIFT)) & FLEXCAN_ETDC_ETDCVAL_MASK) /* Constructs the ETDCVAL field value */
/*
 *  This field holds the enhanced transceiver delay compensation value.
 */
#define FLEXCAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)     /* Mask for the ETDCOFF field */
#define FLEXCAN_ETDC_ETDCOFF_SHIFT                   (16U)           /* Shift value for the ETDCOFF field */
#define FLEXCAN_ETDC_ETDCOFF(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ETDC_ETDCOFF_SHIFT)) & FLEXCAN_ETDC_ETDCOFF_MASK) /* Constructs the ETDCOFF field value */
/*
 *  This field defines the enhanced transceiver delay compensation offset.
 */
#define FLEXCAN_ETDC_TDMDIS_MASK                     (0x40000000U)   /* Mask for the TDMDIS field */
#define FLEXCAN_ETDC_TDMDIS_SHIFT                    (30U)           /* Shift value for the TDMDIS field */
#define FLEXCAN_ETDC_TDMDIS(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ETDC_TDMDIS_SHIFT)) & FLEXCAN_ETDC_TDMDIS_MASK) /* Constructs the TDMDIS field value */
/*
 *  This bit disables transceiver delay measurement.
 */
#define FLEXCAN_ETDC_ETDCEN_MASK                     (0x80000000U)   /* Mask for the ETDCEN field */
#define FLEXCAN_ETDC_ETDCEN_SHIFT                    (31U)           /* Shift value for the ETDCEN field */
#define FLEXCAN_ETDC_ETDCEN(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ETDC_ETDCEN_SHIFT)) & FLEXCAN_ETDC_ETDCEN_MASK) /* Constructs the ETDCEN field value */
/*
 *  This bit enables or disables enhanced transceiver delay compensation.
 */



#define FLEXCAN_ERFCR_ERFWM_MASK                     (0x1FU)         /* Mask for the ERFWM field */
#define FLEXCAN_ERFCR_ERFWM_SHIFT                    (0U)            /* Shift value for the ERFWM field */
#define FLEXCAN_ERFCR_ERFWM(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFCR_ERFWM_SHIFT)) & FLEXCAN_ERFCR_ERFWM_MASK) /* Constructs the ERFWM field value */
/*
 *  This field defines the watermark for the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFCR_NFE_MASK                       (0x3F00U)       /* Mask for the NFE field */
#define FLEXCAN_ERFCR_NFE_SHIFT                      (8U)            /* Shift value for the NFE field */
#define FLEXCAN_ERFCR_NFE(x)                         (((uint32)(((uint32)(x)) << FLEXCAN_ERFCR_NFE_SHIFT)) & FLEXCAN_ERFCR_NFE_MASK) /* Constructs the NFE field value */
/*
 *  This field defines the number of filters for the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFCR_NEXIF_MASK                     (0x7F0000U)     /* Mask for the NEXIF field */
#define FLEXCAN_ERFCR_NEXIF_SHIFT                    (16U)           /* Shift value for the NEXIF field */
#define FLEXCAN_ERFCR_NEXIF(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFCR_NEXIF_SHIFT)) & FLEXCAN_ERFCR_NEXIF_MASK) /* Constructs the NEXIF field value */
/*
 *  This field defines the number of extended ID filters.
 */
#define FLEXCAN_ERFCR_DMALW_MASK                     (0x7C000000U)   /* Mask for the DMALW field */
#define FLEXCAN_ERFCR_DMALW_SHIFT                    (26U)           /* Shift value for the DMALW field */
#define FLEXCAN_ERFCR_DMALW(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFCR_DMALW_SHIFT)) & FLEXCAN_ERFCR_DMALW_MASK) /* Constructs the DMALW field value */
/*
 *  This field configures the DMA last word behavior.
 */
#define FLEXCAN_ERFCR_ERFEN_MASK                     (0x80000000U)   /* Mask for the ERFEN field */
#define FLEXCAN_ERFCR_ERFEN_SHIFT                    (31U)           /* Shift value for the ERFEN field */
#define FLEXCAN_ERFCR_ERFEN(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFCR_ERFEN_SHIFT)) & FLEXCAN_ERFCR_ERFEN_MASK) /* Constructs the ERFEN field value */
/*
 *  This bit enables or disables the enhanced Rx FIFO.
 */



#define FLEXCAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)   /* Mask for the ERFDAIE field */
#define FLEXCAN_ERFIER_ERFDAIE_SHIFT                 (28U)           /* Shift value for the ERFDAIE field */
#define FLEXCAN_ERFIER_ERFDAIE(x)                    (((uint32)(((uint32)(x)) << FLEXCAN_ERFIER_ERFDAIE_SHIFT)) & FLEXCAN_ERFIER_ERFDAIE_MASK) /* Constructs the ERFDAIE field value */
/*
 *  This bit enables or disables the enhanced Rx FIFO data available interrupt.
 */
#define FLEXCAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)   /* Mask for the ERFWMIIE field */
#define FLEXCAN_ERFIER_ERFWMIIE_SHIFT                (29U)           /* Shift value for the ERFWMIIE field */
#define FLEXCAN_ERFIER_ERFWMIIE(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_ERFIER_ERFWMIIE_SHIFT)) & FLEXCAN_ERFIER_ERFWMIIE_MASK) /* Constructs the ERFWMIIE field value */
/*
 *  This bit enables or disables the enhanced Rx FIFO watermark indication interrupt.
 */
#define FLEXCAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)   /* Mask for the ERFOVFIE field */
#define FLEXCAN_ERFIER_ERFOVFIE_SHIFT                (30U)           /* Shift value for the ERFOVFIE field */
#define FLEXCAN_ERFIER_ERFOVFIE(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_ERFIER_ERFOVFIE_SHIFT)) & FLEXCAN_ERFIER_ERFOVFIE_MASK) /* Constructs the ERFOVFIE field value */
/*
 *  This bit enables or disables the enhanced Rx FIFO overflow interrupt.
 */
#define FLEXCAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)   /* Mask for the ERFUFWIE field */
#define FLEXCAN_ERFIER_ERFUFWIE_SHIFT                (31U)           /* Shift value for the ERFUFWIE field */
#define FLEXCAN_ERFIER_ERFUFWIE(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_ERFIER_ERFUFWIE_SHIFT)) & FLEXCAN_ERFIER_ERFUFWIE_MASK) /* Constructs the ERFUFWIE field value */
/*
 *  This bit enables or disables the enhanced Rx FIFO underflow interrupt.
 */



#define FLEXCAN_ERFSR_ERFEL_MASK                     (0x3FU)         /* Mask for the ERFEL field */
#define FLEXCAN_ERFSR_ERFEL_SHIFT                    (0U)            /* Shift value for the ERFEL field */
#define FLEXCAN_ERFSR_ERFEL(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFEL_SHIFT)) & FLEXCAN_ERFSR_ERFEL_MASK) /* Constructs the ERFEL field value */
/*
 *  This field indicates the number of elements in the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFSR_ERFF_MASK                      (0x10000U)      /* Mask for the ERFF field */
#define FLEXCAN_ERFSR_ERFF_SHIFT                     (16U)           /* Shift value for the ERFF field */
#define FLEXCAN_ERFSR_ERFF(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFF_SHIFT)) & FLEXCAN_ERFSR_ERFF_MASK) /* Constructs the ERFF field value */
/*
 *  This bit indicates that the enhanced Rx FIFO is full.
 */
#define FLEXCAN_ERFSR_ERFE_MASK                      (0x20000U)      /* Mask for the ERFE field */
#define FLEXCAN_ERFSR_ERFE_SHIFT                     (17U)           /* Shift value for the ERFE field */
#define FLEXCAN_ERFSR_ERFE(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFE_SHIFT)) & FLEXCAN_ERFSR_ERFE_MASK) /* Constructs the ERFE field value */
/*
 *  This bit indicates that the enhanced Rx FIFO is empty.
 */
#define FLEXCAN_ERFSR_ERFCLR_MASK                    (0x8000000U)    /* Mask for the ERFCLR field */
#define FLEXCAN_ERFSR_ERFCLR_SHIFT                   (27U)           /* Shift value for the ERFCLR field */
#define FLEXCAN_ERFSR_ERFCLR(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFCLR_SHIFT)) & FLEXCAN_ERFSR_ERFCLR_MASK) /* Constructs the ERFCLR field value */
/*
 *  This bit clears the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFSR_ERFDA_MASK                     (0x10000000U)   /* Mask for the ERFDA field */
#define FLEXCAN_ERFSR_ERFDA_SHIFT                    (28U)           /* Shift value for the ERFDA field */
#define FLEXCAN_ERFSR_ERFDA(x)                       (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFDA_SHIFT)) & FLEXCAN_ERFSR_ERFDA_MASK) /* Constructs the ERFDA field value */
/*
 *  This bit indicates that data is available in the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFSR_ERFWMI_MASK                    (0x20000000U)   /* Mask for the ERFWMI field */
#define FLEXCAN_ERFSR_ERFWMI_SHIFT                   (29U)           /* Shift value for the ERFWMI field */
#define FLEXCAN_ERFSR_ERFWMI(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFWMI_SHIFT)) & FLEXCAN_ERFSR_ERFWMI_MASK) /* Constructs the ERFWMI field value */
/*
 *  This bit indicates that the watermark has been reached in the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFSR_ERFOVF_MASK                    (0x40000000U)   /* Mask for the ERFOVF field */
#define FLEXCAN_ERFSR_ERFOVF_SHIFT                   (30U)           /* Shift value for the ERFOVF field */
#define FLEXCAN_ERFSR_ERFOVF(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFOVF_SHIFT)) & FLEXCAN_ERFSR_ERFOVF_MASK) /* Constructs the ERFOVF field value */
/*
 *  This bit indicates an overflow in the enhanced Rx FIFO.
 */
#define FLEXCAN_ERFSR_ERFUFW_MASK                    (0x80000000U)   /* Mask for the ERFUFW field */
#define FLEXCAN_ERFSR_ERFUFW_SHIFT                   (31U)           /* Shift value for the ERFUFW field */
#define FLEXCAN_ERFSR_ERFUFW(x)                      (((uint32)(((uint32)(x)) << FLEXCAN_ERFSR_ERFUFW_SHIFT)) & FLEXCAN_ERFSR_ERFUFW_MASK) /* Constructs the ERFUFW field value */
/*
 *  This bit indicates an underflow in the enhanced Rx FIFO.
 */



#define FLEXCAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)   /* Mask for the FEL field */
#define FLEXCAN_ERFFEL_FEL_SHIFT                     (0U)            /* Shift value for the FEL field */
#define FLEXCAN_ERFFEL_FEL(x)                        (((uint32)(((uint32)(x)) << FLEXCAN_ERFFEL_FEL_SHIFT)) & FLEXCAN_ERFFEL_FEL_MASK) /* Constructs the FEL field value */
/*
 *  This register defines the filter element for the enhanced Rx FIFO.
 */


#define FLEXCAN_ERFFEL_FEL_FSCH_MASK                 (0xC0000000U)
#define FLEXCAN_ERFFEL_FEL_FSCH_SHIFT                (30U)
#define FLEXCAN_ERFFEL_FEL_FSCH(x)                   (((uint32)(((uint32)(x)) << FLEXCAN_ERFFEL_FEL_FSCH_SHIFT)) & FLEXCAN_ERFFEL_FEL_FSCH_MASK)

#define FLEXCAN_ERFFEL_FEL_STD_FILTER1_MASK          (0x7FF0000U)
#define FLEXCAN_ERFFEL_FEL_STD_FILTER1_SHIFT         (16U)
#define FLEXCAN_ERFFEL_FEL_STD_FILTER1(x)            (((uint32)(((uint32)(x)) << FLEXCAN_ERFFEL_FEL_STD_FILTER1_SHIFT)) & FLEXCAN_ERFFEL_FEL_STD_FILTER1_MASK)
#define FLEXCAN_ERFFEL_FEL_STD_FILTER2_MASK          (0x7FFU)
#define FLEXCAN_ERFFEL_FEL_STD_FILTER2_SHIFT         (0U)
#define FLEXCAN_ERFFEL_FEL_STD_FILTER2(x)            (((uint32)(((uint32)(x)) << FLEXCAN_ERFFEL_FEL_STD_FILTER2_SHIFT)) & FLEXCAN_ERFFEL_FEL_STD_FILTER2_MASK)

#define FLEXCAN_ERFFEL_FEL_EXT_FILTER_MASK          (0x1FFFFFFFU)
#define FLEXCAN_ERFFEL_FEL_EXT_FILTER_SHIFT         (0U)
#define FLEXCAN_ERFFEL_FEL_EXT_FILTER(x)            (((uint32)(((uint32)(x)) << FLEXCAN_ERFFEL_FEL_EXT_FILTER_SHIFT)) & FLEXCAN_ERFFEL_FEL_EXT_FILTER_MASK)
/* The count of CAN_ERFFEL */
#define FLEXCAN_ERFFEL_COUNT                         (128U)

#define FLEXCAN_ENHANCED_RX_FIFO_OFFSET              (0x2000U)
#define FLEXCAN_ENHANCED_RX_FIFO_INIT_FLAG           (FLEXCAN_ERFSR_ERFDA_MASK | FLEXCAN_ERFSR_ERFWMI_MASK | FLEXCAN_ERFSR_ERFOVF_MASK | FLEXCAN_ERFSR_ERFOVF_MASK)

#define APB_PSLVERR_INT_STAT_MASK                (0x200000U)

#define APB_PSLVERR_INT_STAT_EN_MASK             (0x200000U)

#ifdef __cplusplus
}
#endif
#endif /* CAN_IP_REG_H_ */
